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LAN91C111 Datasheet, PDF (121/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY | |||
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LAN91C111
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1: REVISION HISTORY
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY
CORRECTION
DS00002276A (09-01-16)
Rev. 1.92 (06-27-11)
Rev. 1.91 (06-01-09)
Replaces previous SMSC version Rev. 1.92 (06-27-11)
Section 7.7.17, "PHY
Powerdown," on page 36
Added note stating that the PDN bit must not be
set when the device is in external PHY mode.
Table 10-1, âTypical Flow Of
Events For Placing Device
In Low Power Mode,â on
page 77
Added note to step 6 stating that the bit (PDN)
must not be set when the device is in external PHY
mode.
Table 10-2, âFlow Of Events
For Restoring Device In
Normal Power Mode,â on
page 78
Added note to step 3 stating that the step is only
performed when the device is in internal PHY
mode.
Table 9.1, âRegister 0.
Control Register,â on
page 69
Added note to PDN bit definition stating that the bit
must not be set when the device is in external PHY
mode.
The following ordering information has been removed: âLAN91C111-NC,
LAN91C111i-NC (Industrial Temperature) for 128 pin QFP packagesâ,
âLAN91C111-NE, LAN91C111i-NE (Industrial Temperature) for 128-pin TQFP
packagesâ as these has been discontinued.
All
Updated document references to Rev. C.
Section 13.1, "Maximum
Ratings*," on page 97
Fixed commercial temp range to state â0ï°C to
+70ï°C for LAN91C111â
Cover
Added bullet: âCommercial Temperature Range
from 0ï°C to 70ï°C (LAN91C111)â
Section 8.24, "Bank 3 -
Revision Register," on
page 62
Changed REV default from â0001â to â0010â
Table 14-3, âAsynchronous
Cycle - nADS=0,â on
page 104
Changed T1A time in table under figure from 10nS
min to 2nS min.
Section 10.4, "Typical Flow
of Event For Receive," on
page 80
In step 4, changed last sentence from âIf CRC is
incorrect the packet memory is released and no
interrupt will occur.â, to âThe RCV_BAD bit of the
Bank 1 Control Register controls whether or not to
generate interrupts when bad CRC packets are
received.â
Section 7.7.14, "Receive
Polarity Correction," on
page 35
Added note at end of 10 Mbps subsection stating
âThe first 3 received packets must be discarded
after the correction of a reverse polarity condition.â
DS00002276A-page 120
ï£ 2011-2016 Microchip Technology Inc.
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