LAN91C111 Datasheet, PDF (68/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

9.1 Register 0. Control Register
LAN91C111
RST
RW, SC
0
LPBK
RW
0
SPEED
RW
1
ANEG_EN
RW
1
PDN
RW
0
MII_DIS
RW
1
ANEG_RST
RW. SC
0
DPLX
RW
0
COLST
RW
0
Reserved
RW
0
Reserved
RW
0
Reserved
RW
0
Reserved
RW
0
Reserved
RW
0
Reserved
RW
0
Reserved
RW
0
9.1.1 RST - RESET
A ‘1’ written to this bit will initiate a reset of the PHY. The bit is self-clearing, and the PHY will return a ‘1’ on reads to this
bit until the reset is completed. Write transactions to this register may be ignored while the PHY is processing the reset.
All PHY registers will be driven to their default states after a reset. The internal PHY is ready for normal operation 50
mS after the RST bit is set. Software driver requires to wait for 50mS after setting the RST bit to high to access the
internal PHY again.
9.1.2
LPBK - Loopback
Writing a ‘1’ will put the PHY into loopback mode.
9.1.3 SPEED (SPEED SELECTION)
When Auto-Negotiation is disabled this bit can be used to manually select the link speed. Writing a ‘1’ to this bit selects
100 Mbps, a ‘0’ selects 10 Mbps.
When Auto-Negotiation is enabled reading or writing this bit has no meaning/effect.
9.1.4 ANEN_EN - AUTO-NEGOTIATION ENABLE
Auto-Negotiation (ANEG) is on when this bit is ‘1’. In that case the contents of bits Speed and Duplex are ignored and
the ANEG process determines the link configuration.
9.1.5 PDN - POWER DOWN
Setting this bit to ‘1’ will put the PHY in PowerDown mode. In this state the PHY will respond to management transac-
tions.
Note: This bit must not be set when the device is in external PHY mode.
9.1.6 MII_DIS - MII DISABLE
Setting this bit will set the PHY to an isolated mode in which it will respond to MII management frames over the MII
management interface but will ignore data on the MII data interface. The internal PHY is placed in isolation mode at
power up and reset. It can be removed from isolation mode by clearing the MII_DIS bit in the PHY Control Register. If
necessary, the internal PHY can be enabled by clearing the EXT_PHY bit in the Configuration Register.
9.1.7 ANEG_RST - AUTO-NEGOTIATION RESET
This bit will return 0 if the PHY does not support ANEG or if ANEG is disabled through the ANEG_EN bit. If neither of
the previous is true, setting this bit to ‘1’ resets the ANEG process. This bit is self clearing and the PHY will return a ‘1’
until ANEG is initiated, writing a ‘0’ does not affect the ANEG process.
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DS00002276A-page 69