LAN91C111 Datasheet, PDF (76/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
10.0 SOFTWARE DRIVER AND HARDWARE SEQUENCE FLOW
10.1 Software Driver and Hardware Sequence Flow for Power Management
This section describes the sequence of events and the interaction between the Host Driver and the Ethernet controller
to perform power management. The Ethernet controller has the ability to reduce its power consumption when the Device
is not required to receive or transmit Ethernet Packets.
Power Management is obtained by disabling the EPH clocks, including the Clocks derived from the Internal PHY block
to reduce internal switching, this reducing current consumption.
The Host interface however, will still be accessible. As discussed in Table 10-1 and Table 10-2, the tables describe the
interaction between the EPH and Host driver allowing the Device to transition from low power state to normal function-
ality and vice versa.
TABLE 10-1: TYPICAL FLOW OF EVENTS FOR PLACING DEVICE IN LOW POWER MODE
S/W Driver
Controller Function
1 Disable Transmitter – Clear the TXENA bit of the
Transmit Control Register
Ethernet MAC finishes packet currently being
transmitted.
2 Remove and release all TX completion packet
numbers on the TX completion FIFO.
3 Disable Receiver – Clear the RXEN bit of the
Receive Control Register.
The receiver completes receiving the current frame, if
any, and then goes idle. Ethernet MAC will no longer
receive any packets.
4 Process all Received packets and Issue a Remove RX and TX completion FIFO’s are now Empty and
and Release command for each respective RX
all MMU packet numbers are now free.
packet buffer.
5 Disable Interrupt sources – Clear the Interrupt
Status Register
Save Device Context – Save all Specific Register
Values set by the driver.
6 Set PDN bit in PHY MI Register 0 to 1
Note: This bit must not be set when the device is
in external PHY mode.
7
The internal PHY entered in powerdown mode, the
TP outputs are in high impedance state.
8 Write to the “EPH Power EN” Bit located in the
configuration register, Bank 1 Offset 0.
9
Ethernet MAC gates the RX Clock, TX clock derived
from the Internal PHY. The EPH Clock is also
disabled.
10 The Ethernet MAC is now in low power mode. The
Host may access all Runtime IO mapped registers.
All IO registers are still accessible. However, the
Host should not read or write to the registers with
the exception of:
Configuration Register
Control Register
Bank Register
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DS00002276A-page 77