LAN91C111 Datasheet, PDF (101/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
14.0 TIMING DIAGRAMS
FIGURE 14-1:
ASYNCHRONOUS CYCLE - NADS=0
Address, AEN, nBE[3:0]
nADS
Read Data
nRD, nWR
Write Data
t2
Valid
t3
t4
Valid
t6
t1
t5
t5A
Valid
Parameter
MIN TYP MAX Units
t1
A1-A15, AEN, nBE[3:0] Valid to nRD, nWR Active
2
ns
t2
A1-A15, AEN, nBE[3:0] Hold After nRD, nWR Inactive (Assuming 5
ns
nADS Tied Low)
t3
nRD Low to Valid Data
15
ns
t4
nRD High to Data Invalid
2
15
ns
t5
Data Setup to nWR Inactive
10
ns
t5A
Data Hold After nWR Inactive
5
ns
t6
nRD Strobe Width
15
ns
DS00002276A-page 102
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