LAN91C111 Datasheet, PDF (51/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
8.14 Bank 1 - General Purpose Register
OFFSET
A
NAME
GENERAL PURPOSE
REGISTER
TYPE
READ/WRITE
SYMBOL
GPR
HIGH
BYTE
HIGH DATA BYTE
0
0
0
0
0
0
0
0
LOW
BYTE
LOW DATA BYTE
0
0
0
0
0
0
0
0
This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be used by the
software driver. The storage is word oriented, and the EEPROM word address to be read or written is specified using
the six lowest bits of the Pointer Register.
This register can also be used to sequentially program the Individual Address area of the EEPROM, that is normally
protected from accidental Store operations.
This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is
set. This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C111.
8.15 Bank 1 - Control Register
OFFSET
C
NAME
CONTROL REGISTER
TYPE
READ/WRITE
SYMBOL
CTR
HIGH
BYTE
LOW BYTE
Reserved
0
LE
ENABLE
0
RCV_
BAD
0
CR
ENABLE
0
Reserved
0
TE
ENABLE
0
Reserved
1
Reserved
1
AUTO Reserved
RELEASE
0
0
Reserved EEPROM
SELECT
0
0
Reserved
1
RELOAD
0
Reserved
0
STORE
0
RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate interrupts and
their memory is released.
AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful
(when TX_SUC is set). In that case there is no status word associated with its packet number, and successful packet
numbers are not even written into the TX COMPLETION FIFO. A sequence of transmit packets will generate an interrupt
only when the sequence is completely transmitted (TX EMPTY INT will be set), or when a packet in the sequence expe-
riences a fatal error (TX INT will be set). Upon a fatal error TXENA is cleared and the transmission sequence stops. The
packet number that failed, is present in the FIFO PORTS register, and its pages are not released, allowing the CPU to
restart the sequence after corrective action is taken.
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DS00002276A-page 51