LAN91C111 Datasheet, PDF (49/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
GPCNTRL - This bit is a general purpose output port. Its inverse value drives pin nCNTRL and it is typically connected
to a SELECT pin of the external PHY device such as a power enable. It can be used to select the signaling mode for
the external PHY or as a general purpose non-volatile configuration pin. Defaults low.
EXT PHY – External PHY Enabled.
This bit, when set (1):
a) Enables the external MII.
b) The Internal PHY is disabled and is disconnected (Tri-stated from the internal MII along with any sideband signals
(such as MDINT) going to the MAC Core).
When this bit is cleared (0 - Default):
a) The internal PHY is enabled.
b) The external MII pins, including the MII Management interface pins are tri-stated.
Reserved – Reserved bits.
8.12 Bank 1 - Base Address Register
OFFSET
2
NAME
BASE ADDRESS
REGISTER
TYPE
SYMBOL
READ/WRITE
BAR
This register holds the I/O address decode option chosen for the LAN91C111. It is part of the EEPROM saved setup
and is not usually modified during run-time.
HIGH
A15
A14
A13
A9
A8
A7
A6
A5
BYTE
0
0
0
1
1
0
0
0
LOW
BYTE
Reserved
Reserved
0
0
0
0
0
0
0
1
A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the IOBASE for the
LAN91C111‘s registers. The 64k I/O space is fully decoded by the LAN91C111 down to a 16 location space, therefore
the unspecified address lines A4, A10, A11 and A12 must be all zeros.
All bits in this register are loaded from the serial EEPROM. The I/O base decode defaults to 300h (namely, the high byte
defaults to 18h).
Reserved – Reserved bits.
Below chart shows the decoding of I/O Base Address 300h:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
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DS00002276A-page 49