LAN91C111 Datasheet, PDF (24/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
TABLE 7-1: 4B/5B SYMBOL MAPPING (CONTINUED)
Symbol Name
F
I
J
K
T
R
H
---
Description
Data F
Idle
SSD #1
SSD #2
ESD #1
ESD #2
Halt
Invalid codes
5B Code
11101
11111
11000
10001
01101
00111
00100
All others*
4B Code
1111
0000
0101
0101
0000
0000
Undefined
0000*
* These 5B codes are not used. For decoder, these 5B codes are decoded to 4B 0000. For encoder, 4B 0000 is encoded
to 5B 11110, as shown in symbol Data 0.
The 4B5B decoder detects SSD, ESD and codeword errors in the incoming data stream as specified in IEEE 802.3.
These errors are indicated by asserting RX_ER output while the errors are being transmitted across RXD[3:0], and they
are also indicated in the serial port by setting SSD, ESD, and codeword error bits in the PHY MI serial port Status Output
register.
7.7.3.2 Manchester Decoder - 10 Mbps
In Manchester coded data, the first half of the data bit contains the complement of the data, and the second half of the
data bit contains the true data. The Manchester decoder in the LAN91C111 converts the Manchester encoded data
stream from the TP receiver into NRZ data for the controller interface by decoding the data and stripping off the SOI
pulse. Since the clock and data recovery block has already separated the clock and data from the TP receiver, the Man-
chester decoding process to NRZ data is inherently performed by that block.
7.7.4 CLOCK AND DATA RECOVERY
7.7.4.1 Clock Recovery - 100 Mbps
Clock recovery is done with a PLL. If there is no valid data present on the TP inputs, the PLL is locked to the 25 MHz
TX25. When valid data is detected on the TP inputs with the squelch circuit and when the adaptive equalizer has settled,
the PLL input is switched to the incoming data on the TP input. The PLL then recovers a clock by locking onto the tran-
sitions of the incoming signal from the twisted pair wire. The recovered dock frequency is a 25 MHz nibble dock, and
that clock is outputted on the controller interface signal RX25.
7.7.4.2 Data Recovery - 100 Mbps
Data recovery is performed by latching in data from the TP receiver with the recovered clock extracted by the PLL. The
data is then converted from a single bit stream into nibble wide data word according to the format shown in Figure 7-2.
7.7.4.3 Clock Recovery - 10 Mbps
The clock recovery process for 10Mbps mode is identical to the 100Mbps mode except, (1) the recovered clock fre-
quency is 2.5 MHz nibble clock, (2) the PLL is switched from TX25 to the TP input when the squelch indicates valid data,
(3) The PLL takes up to 12 transitions (bit times) to lock onto the preamble, so some of the preamble data symbols are
lost, but the dock recovery block recovers enough preamble symbols to pass at least 6 nibbles of preamble to the
receive controller interface as shown in Figure 7-2.
7.7.4.4 Data Recovery - 10 Mbps
The data recovery process for 10Mbps mode is identical to the 100Mbps mode. As mentioned in the Manchester
Decoder section, the data recovery process inherently performs decoding of Manchester encoded data from the TP
inputs.
DS00002276A-page 24
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