LAN91C111 Datasheet, PDF (30/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
rity, link pulses are used for that in 10 Mbps mode, (5) start of packet is determined when the receiver goes into the
unsquelch state an a CRS100 is asserted, and (6) the receiver meets the squelch requirements defined in IEEE 802.3
Clause 14.
7.7.8.5 Equalizer Disable
The adaptive equalizer can be disabled by setting the equalizer disable bit in the PHY Ml serial port Configuration 1
register. When disabled, the equalizer is forced into the response it would normally have if zero cable length was
detected.
7.7.8.6 Receive Level Adjust
The receiver squelch and unsquelch levels can be lowered by 4.5 dB by setting the receive level adjust bit in the PHY
Ml serial port Configuration 1 register. By setting this bit, the device may be able to support longer cable lengths.
7.7.9 COLLISION
7.7.9.1 100 Mbps
Collision occurs whenever transmit and receive occur simultaneously while the device is in Half Duplex.
Collision is sensed whenever there is simultaneous transmission (packet transmission on TPO±) and reception (non-
idle symbols detected on TP input). When collision is detected, the MAC is notified. Once collision starts, the receive
and transmit packets that caused the collision are terminated by their respective MACs until the responsible MACs ter-
minate the transmission, the PHY continues to pass the data on.
The collision function is disabled if the device is in the Full Duplex mode, is in the Link Fail State, or if the device is in
the diagnostic loopback mode.
7.7.9.2 10 Mbps
Collision in 10Mbps mode is identical to the 100Mbps mode except, (1) reception is determined by the 10Mbps squelch
criteria, (2) data being passed to the MAC are forced to all 0's, (3) MAC is notified of the collision when the SQE test is
performed, (4) MAC is notified of the collision when the jabber condition has been detected.
7.7.9.3 Collision Test
The MAC and PHY collision indication can be tested by setting the collision test register bit in the PHY MI serial port
Control register. When this bit is set, internal TXEN from the MAC is looped back onto COL and the TP outputs are
disabled.
7.7.10 START OF PACKET
7.7.10.1 100 Mbps
Start of packet for 100 Mbps mode is indicated by a unique Start of Stream Delimiter (referred to as SSD). The SSD
pattern consists of the two /J/K/ 5B symbols inserted at the beginning of the packet in place of the first two preamble
symbols, as defined in IEEE 802.3 Clause 24.
The transmit SSD is generated by the 4B5B encoder and the /J/K/ symbols are inserted by the 4B5B encoder at the
beginning of the transmit data packet in place of the first two 5B symbols of the preamble.
The receive pattern is detected by the 4B5B decoder by examining groups of 10 consecutive code bits (two 5B words)
from the descrambler. Between packets, the receiver will be detecting the idle pattern, which is 5B /I/ symbols. While in
the idle state, the MAC is notified that no data/invalid data is received.
If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of the /J/K/ symbols, the start
of packet is detected, data reception is begun, the MAC is notified that valid data is received, and 5/5/ symbols are sub-
stituted in place of the /J/K/ symbols.
If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /I/I/
nor /J/K/ symbols but contains at least 2 non contiguous 0's, then activity is detected but the start of packet is considered
to be faulty and a False Carrier Indication (also referred to as bad SSD) is signaled to the controller interface. When
False Carrier is detected, the MAC is notified of false carrier and invalid received, and the bad SSD bit is set in the PHY
Ml serial port Status Output register. Once a False Carrier Event is detected, the idle pattern (two /I/I/ symbols) must be
detected before any new SSD's can be sensed.
DS00002276A-page 30
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