LAN91C111 Datasheet, PDF (58/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
OFFSET
C
NAME
INTERRUPT
ACKNOWLEDGE
REGISTER
TYPE
SYMBOL
WRITE ONLY
IST
MDINT
Reserved
RX_OVRN
INT
TX EMPTY
INT
TX INT
OFFSET
D
NAME
INTERRUPT MASK
REGISTER
TYPE
SYMBOL
READ/WRITE
MSK
MDINT
MASK
0
Reserved
0
EPH INT
MASK
0
RX_OVRN
INT
MASK
ALLOC INT
MASK
TX EMPTY
INT
MASK
0
0
0
TX INT
MASK
0
RCV INT
MASK
0
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A MASK bit being
set will cause a hardware interrupt.
MDINT - Set when the following bits in the PHY MI Register 18 (Serial Port Status Output Register) change state.
1. LNKFAIL, 2) LOSSSYNC, 3) CWRD, 4) SSD, 5) ESD, 6) PROL, 7) JAB, 8) SPDDET, 9) DPLXDET.
These bits automatically latch upon changing state and stay latched until they are read. When they are read, the bits
that caused the interrupt to happen are updated to their current value. The MDINT bit will be cleared by writing the
acknowledge register with MDINT bit set.
Reserved - Must be 0
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special conditions. This
bit merges exception type of interrupt sources, whose service time is not critical to the execution speed of the low level
drivers. The exact nature of the interrupt can be obtained from the EPH Status Register (EPHSR), and enabling of these
sources can be done via the Control Register. The possible sources are:
LINK - Link Test transition
CTR_ROL - Statistics counter roll over
TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and the specific rea-
son will be reflected by the bits:
• SQET - SQE Error
• LOST CARR - Lost Carrier
• LATCOL - Late Collision
• 16COL - 16 collisions
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register.
• LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error Enable)
DS00002276A-page 58
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