LAN91C111 Datasheet, PDF (8/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
FIGURE 3-2:
BLOCK DIAGRAM
EEPROM
INTERFACE
MII
Control
Address
8-32 bit
Bus
Interface
Unit
Control
Control
Control
Arbiter
Control
MMU
TX/RX
FIFO
Pointer
Control
Control
DMA
Ethernet
Protocol
Handler
(EPH)
TPO
10/100
PHY
Data
WR
FIFO
RD
FIFO
8K Byte
Dynamically
Allocated
SRAM
32-bit Data
32-bit Data
TX Data
RX Data
TXD[0-3]
TPI
RXD[0-3]
The diagram shown in Figure 3-2 describes the supported Host interfaces, which include ISA or Generic Embedded.
The Host interface is an 8, 16 or 32 bit wide address / data bus with extensions for 32, 16 and 8 bit embedded RISC
and ARM processors.
The figure shown next page describes the Microchip LAN91C111 functional blocks required to integrate a 10/100 Ether-
net Physical layer framer to the internal MAC.
DS00002276A-page 8
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