LAN91C111 Datasheet, PDF (105/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
FIGURE 14-5:
BURST WRITE CYCLES - NVLBUS=1
Clock
t12
t17
t22
t18
t14
nDATACS
W/nR
nCYCLE
Write Data
nRDYRTN
t20
a
t20
b
t15
t18
t12A
t17A
t22A
t20
c
t12
t12A
t14
t15
t17
t17A
t18
t20
t22
t22A
Parameter
nDATACS Setup to LCLK Rising
nDATACS Hold After LCLK Rising
nRDYRTN Setup to LCLK Falling
nRDYRTN Hold after LCLK Falling
W/nR Setup to LCLK Falling
W/nR Hold After LCLK Falling
Data Setup to LCLK Rising (Write)
Data Hold from LCLK Rising (Write)
nCYCLE Setup to LCLK Rising
nCYCLE Hold After LCLK Rising
MIN TYP MAX Units
20
ns
0
ns
10
ns
10
ns
15
ns
3
ns
15
ns
4
ns
5
ns
10
ns
DS00002276A-page 106
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