LAN91C111 Datasheet, PDF (47/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
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Try to Manually
Set to ……
100 Full Duplex
100 Half Duplex
10 Full Duplex
10 Half Duplex
Auto-Negotiation
Control Bits
Speed and Duplex Mode Control for the PHY
ANEG
Bit
RPCR
(MAC
Bank 0
Offset A)
0
0
1
0
0
1
0
0
1
0
0
1
ANEG_EN
Bit
Register 0
(PHY)
0
1
0
0
1
0
0
1
0
0
1
0
SPEED
Bit
RPCR
(MAC
Bank 0
Offset A)
1
1
X
1
1
X
0
0
X
0
0
X
DPLX
Bit
RPCR
(MAC
Bank 0
Offset A)
1
1
X
0
0
X
1
1
X
0
0
X
SPEED
Bit
DPLX
Bit
Register 0 Register 0
(PHY)
(PHY)
X
X
X
X
1
1
X
X
X
X
1
0
X
X
X
X
0
1
X
X
X
X
0
0
Duplex
Mode
Control for
the MAC
SWFDUP
Bit
Transmit
Control
Register
(MAC)
1
1
1
0
0
0
1
1
1
0
0
0
LS2A, LS1A, LS0A – LED select Signal Enable. These bits define what LED control signals are routed to the LEDA
output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected.
LS2A LS1A LS0A
LED Select Signal – LEDA
0
0
0
nPLED3+ nPLED0 – Logical OR of 100Mbps Link detected 10Mbps Link detected
(default)
0
0
1
Reserved
0
1
0
nPLED0 - 10Mbps Link detected
0
1
1
nPLED1 - Full Duplex Mode enabled
1
0
0
nPLED2 - Transmit or Receive packet occurred
1
0
1
nPLED3 - 100Mbps Link detected
1
1
0
nPLED4 - Receive packet occurred
1
1
1
nPLED5 - Transmit packet occurred
 2011-2016 Microchip Technology Inc.
DS00002276A-page 47