LAN91C111 Datasheet, PDF (4/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
1.0 GENERAL DESCRIPTION
The Microchip LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity
solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design
requirements. The LAN91C111 is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the
CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16-
bit or 8-bit bus Host interface in embedded applications.
The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive opera-
tions.
The Microchip LAN91C111 is software compatible with the LAN9000 family of products.
Memory management is handled using a patented optimized MMU (Memory Management Unit) architecture and a 32-
bit wide internal data path. This I/O mapped architecture can sustain back-to-back frame transmission and reception for
superior data throughput and optimal performance. It also dynamically allocates buffer memory in an efficient buffer uti-
lization scheme, reducing software tasks and relieving the host CPU from performing these housekeeping functions.
The Microchip LAN91C111 provides a flexible slave interface for easy connectivity with industry-standard buses. The
Bus Interface Unit (BIU) can handle synchronous as well as asynchronous transfers, with different signals being used
for each one. Asynchronous bus support for ISA is supported even though ISA cannot sustain 100 Mbps traffic. Fast
Ethernet data rates are attainable for ISA-based nodes on the basis of the aggregate traffic benefits.
Two different interfaces are supported on the network side. The first Interface is a standard Magnetics transmit/receive
pair interfacing to 10/100Base-T utilizing the internal physical layer block. The second interface follows the MII (Media
Independent Interface) specification standard, consisting of 4 bit wide data transfers at the nibble rate. This interface is
applicable to 10 Mbps standard Ethernet or 100 Mbps Ethernet networks. Three of the LAN91C111’s pins are used to
interface to the two-line MII serial management protocol.
The Microchip LAN91C111 integrates IEEE 802.3 Physical Layer for twisted pair Ethernet applications. The PHY can
be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation. The Analog PHY block
consists of a 4B5B/Manchester encoder/decoder, scrambler/de-scrambler, transmitter with wave shaping and output
driver, twisted pair receiver with on chip equalizer and baseline wander correction, clock and data recovery, Auto-Nego-
tiation, controller interface (MII), and serial port (MI). Internal output wave shaping circuitry and on-chip filters eliminate
the need for external filters normally required in 100Base-TX and 10Base-T applications.
The LAN91C111 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on-chip
Auto-Negotiation algorithm. The LAN91C111 is ideal for media interfaces for embedded application desiring Ethernet
connectivity as well as 100Base-TX/10Base-T adapter cards, motherboards, repeaters, switching hubs. The
LAN91C111 operates from a single 3.3V supply. The inputs and outputs of the host Interface are 5V tolerant and will
directly interface to other 5V devices.
DS00002276A-page 4
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