LAN91C111 Datasheet, PDF (65/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
PHY Register Description:
TABLE 9-1: MII SERIAL FRAME STRUCTURE
<Idle> <Start> <Read> <Write>
IDLE ST[1:0] READ WRITE
<PHY Addr.>
PHYAD[4:0]
<REG.Addr.>
REGAD[4:0]
<Turnaround>
TA[1:0]
<Data>
D[15:0]
D[15:0]

Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 16
Register 17
Register 18
Register 19
Register 20
Control
Status
PHY ID#1
PHY ID#2
Auto-Negotiation Advertisement
Auto-Negotiation Remote End Capability
Configuration 1
Configuration 2
Status Output
Mask
Reserved
Symbol
IDLE
Name
Idle Pattern
ST1
ST0
READ
WRITE
PHYAD[4:0]
REGAD[4:0]
Start Bits
Read Select
Write Select
Physical
Device
Address
Register
Address
Definition
R/W
These bits are an idle pattern. Device will not initiate an MI cycle until W
it detects at least 32 1's
When ST[1:0]=01, a MI Serial Port access cycle starts.
W
1 = Read Cycle
W
1 = Write Cycle
W
PHYSICAL ADDRESS
R
If REGAD[4:0] = 00000-11110, these bits determine the specific
W
register from which D[15:0] is read/written. If multiple register access
is enabled and REGAD[4:0] = 11111, all registers are read/written in
a single cycle.
DS00002276A-page 66
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