LAN91C111 Datasheet, PDF (48/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
LS2B, LS1B, LS0B – LED select Signal Enable. These bits define what LED control signals are routed to the LEDB
output pin on the LAN91C111 Ethernet Controller. The default is 10/100 Link detected.
LS2B LS1B LS0B
LED Select Signal – LEDB
0
0
0
nPLED3+ nPLED0 – Logical OR of 100Mbps Link detected 10Mbps Link detected
(default)
0
0
1
Reserved
0
1
0
nPLED0 - 10Mbps Link detected
0
1
1
nPLED1 – Full Duplex Mode enabled
1
0
0
nPLED2 – Transmit or Receive packet occurred
1
0
1
nPLED3 - 100Mbps Link detected
1
1
0
nPLED4 - Receive packet occurred
1
1
1
nPLED5 - Transmit packet occurred
Reserved – Must be 0.
8.11 Bank 1 - Configuration Register
OFFSET
0
NAME
CONFIGURATION
REGISTER
TYPE
SYMBOL
READ/WRITE
CR
The Configuration Register holds bits that define the adapter configuration and are not expected to change during run-
time. This register is part of the EEPROM saved setup.
HIGH
BYTE
LOW
BYTE
EPH
Power
EN
Reserved Reserved NO Reserved
WAIT
1
0
1
0
0
Reserved Reserved
Reserved
GPCNTRL
0
Reserved
EXT PHY
0
Reserved
Reserved
0
Reserved
1
0
1
1
0
0
0
1
EPH Power EN - Used to selectively power transition the EPH to a low power mode. When this bit is cleared (0), the
Host will place the EPH into a low power mode. The Ethernet MAC will gate the 25Mhz TX and RX clock so that the
Ethernet MAC will no longer be able to receive and transmit packets. The Host interface however, will still be active
allowing the Host access to the device through Standard IO access. All LAN91C111 registers will still be accessible.
However, status and control will not be allowed until the EPH Power EN bit is set AND a RESET MMU command is
initiated.
NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if
not ready for a transfer. When clear, negates ARDY for two to three clocks on any cycle to the LAN91C111.
DS00002276A-page 48
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