LAN91C111 Datasheet, PDF (18/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
complete register has been read/written, the serial shift process is halted, data is latched into the device, and MDIO
goes into high impedance state. Another serial shift cycle cannot be initiated until the idle condition (at least 32 contin-
uous 1's) is detected.
7.5.3 MI SERIAL PORT FRAME STRUCTURE
The structure of the PHY serial port frame is shown in Table 9-1 and timing diagram of a frame is shown in Figure 7-1.
Each serial port access cycle consists of 32 bits (or 192 bits if multiple register access is enabled and
REGAD[4:0]=11111), exclusive of idle. The first 16 bits of the serial port cycle are always write bits and are used for
addressing. The last 16/176 bits are from one/all of the 11 data registers.
The first 2 bit in Table 9-1and Figure 7-1 are start bits and need to be written as a 01 for the serial port cycle to continue.
The next 2 bits are a read and write bit which determine if the accessed data register bits will be read or write. The next
5 bits are device addresses. The next 5 bits are register address select bits, which select one of the five data registers
for access. The next 1 bit is a turnaround bit which is not an actual register bit but extra time to switch MDIO from write
to read if necessary, as shown in Figure 7-1. The final 16 bits of the PHY Ml serial port cycle (or 176 bits if multiple reg-
ister access is enabled and REGAD[4:0]=11111) come from the specific data register designated by the register address
bits REGAD[4:0].
DS00002276A-page 18
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