LAN91C111 Datasheet, PDF (53/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

COMMAND SET:
LAN91C111
Operation
Code
000
001
010
011
100
101
110
111
Decimal
Value
0
1
2
3
4
5
6
7
Command
NOOP - NO OPERATION
ALLOCATE MEMORY FOR TX
RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant
interrupts, resets packet FIFO pointers.
REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has
completed processing of present receive frame. This command removes the
receive packet number from the RX FIFO and brings the next receive frame (if
any) to the RX area (output of RX FIFO).
REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all
memory used by the packet presently at the RX FIFO output. The MMU busy
time after issuing REMOVE and RELEASE command depends on the time when
the busy bit is cleared. The time from issuing REMOVE and RELEASE command
on the last receive packet to the time when receive FIFO is empty depends on
RX INT bit turning low. An alternate approach can be checking the read RX FIFO
register.
RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified
in the PACKET NUMBER REGISTER. Should not be used for frames pending
transmission. Typically used to remove transmitted frames, after reading their
completion status. Can be used following 3) to release receive packet memory in
a more flexible way than 4).
ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of
transmitting a packet just loaded into RAM. The packet number to be enqueued
is taken from the PACKET NUMBER REGISTER.
RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO
holding the packet numbers awaiting transmission and the TX Completion FIFO.
This command provides a mechanism for canceling packet transmissions, and
reordering or bypassing the transmit queue. The RESET TX FIFOs command
should only be used when the transmitter is disabled. Unlike the RESET MMU
command, the RESET TX FIFOs does not release any memory.
Note:
• When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with
outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO
ports register before issuing the command.
• MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet num-
ber has memory allocated to it.
 2011-2016 Microchip Technology Inc.
DS00002276A-page 53