LAN91C111 Datasheet, PDF (12/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
Pin No.
TQFP
38
QFP
40
43
45
46
48
29
31
45
47
31
33
32
34
34
36
9
11
10
12
Name
Symbol
Buffer
Type
Description
Asynchronous ARDY
Ready
OD16
nSynchronous nSRDY
O16
Ready
nReady Return nRDYRTN I**
Interrupt
INTR0
O24
nLocal Device nLDEV
O16
nRead Strobe nRD
IS**
nWrite Strobe nWR
IS**
nData Path
Chip Select
nDATACS I with
pullup**
EEPROM Clock EESK
O4
EEPROM
Select
EECS
O4
Open drain output. ARDY may be used
when interfacing asynchronous buses to
extend accesses. Its rising (access
completion) edge is controlled by the
XTAL1 clock and, therefore,
asynchronous to the host CPU or bus
clock. ARDY is negated during
Asynchronous cycle when one of the
following conditions occurs:
No_Wait Bit in the Configuration Register
is cleared.
Read FIFO contains less than 4 bytes
when read.
Write FIFO is full when write.
Output. This output is used when
interfacing synchronous buses and
nVLBUS=0 to extend accesses. This
signal remains normally inactive, and its
falling edge indicates completion. This
signal is synchronous to the bus clock
LCLK.
Input. This input is used to complete
synchronous read cycles. In EISA burst
mode it is sampled on falling LCLK
edges, and synchronous cycles are
delayed until it is sampled high.
Interrupt Output – Active High, it’s used to
interrupt the Host on a status event. Note:
The selection bits used to determined by
the value of INT SEL 1-0 bits in the
Configuration Register are no longer
required and have been set to reserved in
this revision of the FEAST family of
devices.
Output. This active low output is asserted
when AEN is low and A4-A15 decode to
the LAN91C111 address programmed
into the high byte of the Base Address
Register. nLDEV is a combinatorial
decode of unlatched address and AEN
signals.
Input. Used in asynchronous bus
interfaces.
Input. Used in asynchronous bus
interfaces.
Input. When nDATACS is low, the Data
Path can be accessed regardless of the
values of AEN, A1-A15 and the content of
the BANK SELECT Register. nDATACS
provides an interface for bursting to and
from the LAN91C111 32 bits at a time.
Output. 4 sec clock used to shift data in
and out of the serial EEPROM.
Output. Serial EEPROM chip select.
Used for selection and command framing
of the serial EEPROM.
DS00002276A-page 12
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