LAN91C111 Datasheet, PDF (109/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
FIGURE 14-9:
SYNCHRONOUS READ CYCLE - NVLBUS=0
Clock
Address, AEN, nBE[3:0]
nADS
W/nR
nCYCLE
Read Data
nSRDY
nRDYRTN
t10
t9
Valid
t8
t16
t11
t23
t20
t24
Valid
t21
t21
Parameter
t8
A1-A15, AEN, nBE[3:0] Setup to nADS Rising
t9
A1-A15, AEN, nBE[3:0] Hold After nADS Rising
t10
nCYCLE Setup to LCLK Rising
t11
nCYCLE Hold after LCLK Rising (Non-Burst Mode)
t16
W/nR Setup to nCYCLE Active
t20
Data Hold from LCLK Rising (Read)
t21
nSRDY Delay from LCLK Rising
t23
nRDYRTN Setup to LCLK Rising
t24
nRDYRTN Hold after LCLK Rising
MIN
8
5
5
3
0
4
3
3
TYP MAX
Units
ns
ns
ns
ns
ns
ns
7
ns
ns
ns
DS00002276A-page 110
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