LAN91C111 Datasheet, PDF (31/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /l/l/
nor /J/K/ symbols but does not contain at least 2 non-contiguous 0's, the data is ignored and the receiver stays in the
idle state.
7.7.10.2 10 Mbps
Since the idle period in 10 Mbps mode is defined to be the period when no data is present on the TP inputs, then the
start of packet for 10 Mbps mode is detected when valid data is detected by the TP squelch circuit. When start of packet
is detected, carrier sense signal at internal MII is asserted as described in the Controller Interface section. Refer to the
TP squelch section for 10 Mbps mode for the algorithm for valid data detection.
7.7.11 END OF PACKET
7.7.11.1 100 Mbps
End of packet for 100 Mbps mode is indicated by the End of Stream Delimiter (referred to as ESD). The ESD pattern
consists of the two /T/R/ 4B5B symbols inserted after the end of the packet, as defined in IEEE 802.3 Clause 24.
The transmit ESD is generated by the 4B5B encoder and the /T/R/ symbols are inserted by the 4B5B encoder after the
end of the transmit data packet.
The receive ESD pattern is detected by the 4B5B decoder by examining groups of 10 consecutive code bits (two 5B
words) from the descrambler during valid packet reception to determine if there is an ESD.
If the 10 consecutive code bits from the receiver during valid packet reception consist of the /T/R/ symbols, the end of
packet is detected, data reception is terminated, the MAC is notified of valid data received, and /I/I/ symbols are substi-
tuted in place of the /T/R/ symbols.
If 10 consecutive code bits from the receiver during valid packet reception do not consist of /T/R/ symbols but consist
of /I/I/ symbols instead, then the packet is considered to have been terminated prematurely and abnormally. When this
premature end of packet condition is detected, the MAC is notified of invalid data received for the nibble associated with
the first /I/ symbol. Premature end of packet condition is also indicated by setting the bad ESD bit in the PHY Ml serial
port Status Output register.
7.7.11.2 10 Mbps
The end of packet for 10 Mbps mode is indicated with the SOI (Start of Idle) pulse. The SOI pulse is a positive pulse
containing a Manchester code violation inserted at the end of every packet.
The transmit SOI pulse is generated by the TP transmitter and inserted at the end of the data packet after TXEN is deas-
serted. The transmitted SOI output pulse at the TP output is shaped by the transmit waveshaper to meet the pulse tem-
plate requirements specified in IEEE 802.3 Clause 14 and shown in Figure 7-6.
The receive SOI pulse is detected by the TP receiver by sensing missing data transitions. Once the SOI pulse is
detected, data reception is ended and the MAC is notified of no data/invalid data received.
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DS00002276A-page 31