LAN91C111 Datasheet, PDF (46/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
8.10 Bank 0 - Receive/Phy Control Register
OFFSET
NAME
RECEIVE/PHY CONTROL
A
REGISTER
TYPE
READ/WRITE
SYMBOL
RPCR
HIGH
BYTE
LOW
BYTE
Reserved Reserved SPEED
0
LS2A
0
LS1A
0
LS0A
0
0
0
DPLX
0
LS2B
0
ANEG
0
LS1B
0
Reserved Reserved Reserved
0
LS0B
0
Reserved
0
Reserved
0
0
0
SPEED – Speed select Input. This bit is valid and selects 10/100 PHY operation only when the ANEG Bit = 0, this bit
overrides the SPEED bit in the PHY Register 0 (Control Register) and determine the speed mode. When this bit is set
(1), the Internal PHY will operate at 100Mbps. When this bit is cleared (0), the Internal PHY will operate at 10Mbps.
When the ANEG bit = 1, this bit is ignored and 10/100 operation is determined by the outcome of the Auto-Negotiation
or this bit is overridden by the SPEED bit in the PHY Register 0 (Control Register) when the ANEG_EN bit in the PHY
Register 0 (Control Register) is clear.
DPLX – Duplex Select - This bit selects Full/Half Duplex operation. This bit is valid and selects duplex operation only
when the ANEG Bit = 0, this bit overrides the DPLX bit in the PHY Register 0 (Control Register) and determine the
duplex mode. When this bit is set (1), the Internal PHY will operate at full duplex mode. When this bit is cleared (0), the
Internal PHY will operate at half Duplex mode. When the ANEG bit = 1, this bit is ignored and duplex mode is determined
by the outcome of the Auto-Negotiation or this bit is overridden by the DPLX bit in the PHY Register 0 (Control Register)
when the ANEG_EN bit in the PHY Register 0 (Control Register) is clear.
ANEG – Auto-Negotiation mode select - The PHY is placed in Auto-Negotiation mode when the ANEG bit and the
ANEG_EN bit in PHY Register 0 (Control Register) both are set. When either of these bits is cleared (0), the PHY is
placed in manual mode.
What do you want to
do?
Try to Auto-Negotiate
to ……
100 Full Duplex
100 Half Duplex
10 Full Duplex
10 Half Duplex
Auto-Negotiation
Control Bits
Auto-Negotiation Advertisement Register
Duplex Mode
Control for
the MAC
ANEG ANEG_EN TX_FDX TX_HDX
Bit
Bit
Bit
Bit
10_FDX
Bit
10_HDX
Bit
SWFDUP
Bit
RPCR Register 0 Register 4 Register 4 Register 4 Register 4
(MAC)
(PHY)
(PHY)
(PHY)
(PHY)
(PHY)
Transmit
Control
Register
(MAC)
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
0
0
1
0
DS00002276A-page 46
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