LAN91C111 Datasheet, PDF (73/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
APOLDIS:
JABDIS:
MREG:
INTMDIO:
Reserved:
Auto Polarity Disable
Jabber Disable Select
Multiple Register Access
Enable
Interrupt Scheme Select
Reserved for Factory Use
1 = Auto Polarity Correction 1 = Auto Polarity Correction
Function Disabled
Function Disabled
0 = Normal
0 = Normal
1 = Jabber Disabled RW 1 = Jabber Disabled
0 = Enabled
0 = Enabled
1 = Multiple Register
Access Enabled
0 = No Multiple Register 0 = No Multiple Register
Access
Access
1 = Interrupt Signaled With 1 = Interrupt Signaled With
MDIO Pulse During Idle MDIO Pulse During Idle
0 = Interrupt Not Signaled 0 = Interrupt Not Signaled
On MDIO
On MDIO
9.8 Register 18. Status Output - Structure and Bit Definition
INT
LNKFAIL
LOSSSYNC
CWRD
R
R/LT
R/LT
R/LT
0
0
0
0
SSD
R/LT
0
ESD
R/LT
0
RPOL
R/LT
0
JAB
R/LT
0
SPDDET
R/LT
1
DPLXDET
R/LT
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
DS00002276A-page 74
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