LAN91C111 Datasheet, PDF (17/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
Direct 32 bit access to the Data Path is supported by using the nDATACS input. By asserting nDATACS, external DMA
type of devices will bypass the BIU address decoders and can sequentially access memory with no CPU intervention.
nDATACS accesses can be used in the EISA DMA burst mode (nVLBUS=1) or in asynchronous cycles. These cycles
MUST be 32 bit cycles. Please refer to the corresponding timing diagrams for details on these cycles.
The BIU is implemented using the following principles:
a) Address decoding is based on the values of A15-A4 and AEN.
b) Address latching is performed by using transparent latches that are transparent when nADS=0 and nRD=1,
nWR=1 and latch on nADS rising edge.
c) Byte, word and doubleword accesses to all registers and Data Path are supported except a doubleword write to
offset Ch will only write the BANK SELECT REGISTER (offset 0x0Fh).
d) No bus byte swapping is implemented (no eight bit mode).
e) Word swapping as a function of A1 is implemented for 16 bit bus support.
f) The asynchronous interface uses nRD and nWR strobes. If necessary, ARDY is negated on the leading edge of
the strobe. The ARDY trailing edge is controlled by CLK.
g) The VLBUS synchronous interface uses LCLK, nADS, and W/nR as defined in the VESA specification as well as
nCYCLE to control read and write operations and generate nSRDY.
h) EISA burst DMA cycles to and from the DATA REGISTER are supported as defined in the EISA Slave Mode "C"
specification when nDATACS is driven by nDAK.
i) Synchronous and asynchronous cycles can be mixed as long as they are not active simultaneously.
j) Address and bank selection can be bypassed to generate 32 bit Data Path accesses by activating the nDATACS
pin.
7.5 MAC-PHY Interface
The LAN91C111 integrates the IEEE 802.3 Physical Layer (PHY) and Media Access Control (MAC) into the same sili-
con. The data path connection between the MAC and the internal PHY is provided by the internal MII. The LAN91C111
also supports the EXT_PHY mode for the use of an external PHY, such as HPNA. This mode isolates the internal PHY
to allow interface with an external PHY through the MII pins. To enter this mode, set EXT PHY bit to 1 in the Configura-
tion Register.
7.5.1 MANAGEMENT DATA SOFTWARE IMPLEMENTATION
The MII interface contains of a pair of signals that physically transport the management information across the MII, a
frame format and a protocol specification for exchanging management frames, and a register set that can be read and
written using these frames. MII management refers to the ability of a management entity to communicate with PHY via
the MII serial management interface (MI) for the purpose of displaying, selecting and/or controlling different PHY
options. The host manipulates the MAC to drive the MII management serial interface. By manipulating the MAC's reg-
isters, MII management frames are generated on the management interface for reading or writing information from the
PHY registers. Timing and framing for each management command is to be generated by the CPU (host).
The MAC and external PHY communicate via MDIO and MDC of the MII Management serial interface.
MDIO: Management Data input/output. Bi-directional between MAC and PHY that carries management data. All con-
trol and status information sent over this pin is driven and sampled synchronously to the rising edge of MDC
signal.
MDC:
Management Data Clock. Sourced by the MAC as a timing reference for transfer of information on the MDIO
signal. MDC is a periodic signal with no maximum high or low times. The minimum high and low times should
be 160ns each and the minimum period of the signal should be 400ns. These values are regardless of the nom-
inal period of the TX and RX clocks.
7.5.2 MANAGEMENT DATA TIMING
A timing diagram for a Ml serial port frame is shown in Figure 7-1. The Ml serial port is idle when at least 32 continuous
1's are detected on MDIO and remains idle as long as continuous 1's are detected. During idle, MDIO is in the high
impedance state. When the Ml serial port is in the idle state, a 01 pattern on the MDIO initiates a serial shift cycle. Data
on MDIO is then shifted in on the next 14 rising edges of MDC (MDIO is high impedance). If the register access mode
is not enabled, on the next 16 rising edges of MDC, data is either shifted in or out on MDIO, depending on whether a
write or read cycle was selected with the bits READ and WRITE. After the 32 MDC cycles have been completed, one
 2011-2016 Microchip Technology Inc.
DS00002276A-page 17