LAN91C111 Datasheet, PDF (57/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
8.20 Bank 2 - Data Register
OFFSET
8 THROUGH
BH
NAME
DATA REGISTER
TYPE
SYMBOL
READ/WRITE
DATA
DATA HIGH
X
X
X
X
X
X
X
X
DATA LOW
X
X
X
X
X
X
X
X
DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register.
This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C111 regardless
of whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is
pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte can be accessed
through the Data Low or Data High registers. The order to and from the FIFO is preserved. Byte, word and dword
accesses can be mixed on the fly in any order.
This register is mapped into two consecutive word locations to facilitate double word move operations regardless of the
actual bus width (16 or 32 bits). The DATA register is accessible at any address in the 8 through Bh range, while the
number of bytes being transferred is determined by A1 and nBE0-nBE3. The FIFOs are 12 bytes each.
8.21 Bank 2 - Interrupt Status Registers
OFFSET
C
NAME
INTERRUPT STATUS
REGISTER
TYPE
READ ONLY
SYMBOL
IST
MDINT
0
Reserved
0
EPH INT
0
RX_OVRN ALLOC INT TX EMPTY
INT
INT
0
0
1
TX INT
0
RCV INT
0
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DS00002276A-page 57