PIC18F6390 Datasheet, PDF (81/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
TABLE 5-2: PIC18F6390/6490/8390/8490 REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
SPBRGH1 EUSART1 Baud Rate Generator High Byte
0000 0000 62, 201
BAUDCON1
LCDDATA23⁽⁶⁾
LCDDATA22⁽⁶⁾
ABDOVF
S47C3
S39C3
RCIDL
S46C3
S38C3
—
S45C3
S37C3
SCKP
S44C3
S36C3
BRG16
S43C3
S35C3
—
S42C3
S34C3
WUE
S41C3
S33C3
ABDEN
S40C3
S32C3
01-0 0-00
xxxx xxxx
xxxx xxxx
62, 200
63, 261
63, 261
LCDDATA21
S31C3
S30C3
S29C3
S28C3
S27C3
S26C3
S25C3
S24C3 xxxx xxxx 63, 261
LCDDATA20
S23C3
S22C3
S21C3
S20C3
S19C3
S18C3
S17C3
S16C3 xxxx xxxx 63, 261
LCDDATA19
S15C3
S14C3
S13C3
S12C3
S11C3
S10C3
S09C3
S08C3 xxxx xxxx 63, 261
LCDDATA18
LCDDATA17⁽⁶⁾
LCDDATA16⁽⁶⁾
S07C3
S47C2
S39C2
S06C3
S46C2
S38C2
S05C3
S45C2
S37C2
S04C3
S44C2
S36C2
S03C3
S43C2
S35C2
S02C3
S42C2
S34C2
S01C3
S41C2
S33C2
S00C3
S40C2
S32C2
xxxx xxxx
xxxx xxxx
xxxx xxxx
63, 261
63, 261
63, 261
LCDDATA15
S31C2
S30C2
S29C2
S28C2
S27C2
S26C2
S25C2
S24C2 xxxx xxxx 63, 261
LCDDATA14
S23C2
S22C2
S21C2
S20C2
S19C2
S18C2
S17C2
S16C2 xxxx xxxx 63, 261
LCDDATA13
S15C2
S14C2
S13C2
S12C2
S11C2
S10C2
S09C2
S08C2 xxxx xxxx 63, 261
LCDDATA12
LCDDATA11⁽⁶⁾
S07C2
S47C1
S06C2
S46C1
S05C2
S45C1
S04C2
S44C1
S03C2
S43C1
S02C2
S42C1
S01C2
S41C1
S00C2
S40C1
xxxx xxxx 63, 261
xxxx xxxx 63, 261
SPBRG2
AUSART2 Baud Rate Generator
0000 0000 63, 220
RCREG2
AUSART2 Receive Register
0000 0000 63, 224
TXREG2
AUSART2 Transmit Register
0000 0000 63, 222
TXSTA2
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 0010 63, 218
RCSTA2
LCDDATA10⁽⁶⁾
SPEN
S39C1
RX9
S38C1
SREN
S37C1
CREN
S36C1
ADDEN
S35C1
FERR
S34C1
OERR
S33C1
RX9D
S32C1
0000 000x 63, 219
xxxx xxxx 63, 261
LCDDATA9
S31C1
S30C1
S29C1
S28C1
S27C1
S26C1
S25C1
S24C1 xxxx xxxx 63, 261
LCDDATA8
S23C1
S22C1
S21C1
S20C1
S19C1
S18C1
S17C1
S16C1 xxxx xxxx 63, 261
LCDDATA7
S15C1
S14C1
S13C1
S12C1
S11C1
S10C1
S09C1
S08C1 xxxx xxxx 63, 261
LCDDATA6
LCDDATA5⁽⁶⁾
LCDDATA4⁽⁶⁾
S07C1
S47C0
S39C0
S06C1
S46C0
S38C0
S05C1
S45C0
S37C0
S04C1
S44C0
S36C0
S03C1
S43C0
S35C0
S02C1
S42C0
S34C0
S01C1
S41C0
S33C0
S00C1
S40C0
S32C0
xxxx xxxx
xxxx xxxx
xxxx xxxx
63, 261
63, 261
63, 261
LCDDATA3
S31C0
S30C0
S29C0
S28C0
S27C0
S26C0
S25C0
S24C0 xxxx xxxx 63, 261
LCDDATA2
S23C0
S22C0
S21C0
S20C0
S19C0
S18C0
S17C0
S16C0 xxxx xxxx 63, 261
LCDDATA1
S15C0
S14C0
S13C0
S12C0
S11C0
S10C0
S09C0
S08C0 xxxx xxxx 63, 261
LCDDATA0
LCDSE5⁽²⁾
LCDSE4⁽²⁾
S07C0
SE47
SE39
S06C0
SE46
SE38
S05C0
SE45
SE37
S04C0
SE44
SE36
S03C0
SE43
SE35
S02C0
SE42
SE34
S01C0
SE41
SE33
S00C0
SE40
SE32
xxxx xxxx
0000 0000
0000 0000
63, 261
64, 261
64, 260
LCDSE3
SE31
SE30
SE29
SE28
SE27
SE26
SE25
SE24 0000 0000 64, 261
LCDSE2
SE23
SE22
SE21
SE20
SE19
SE18
SE17
SE16 0000 0000 64, 261
LCDSE1
SE15
SE14
SE13
SE12
SE11
SE10
SE9
SE8 0000 0000 64, 261
LCDSE0
SE7
SE6
SE5
SE4
SE3
SE2
SE1
SE0 0000 0000 64, 261
LCDCON
LCDEN
SLPEN
WERR
—
CS1
CS0
LMUX1
LMUX0 000- 0000 64, 258
LCDPS
WFT
BIASMD
LCDA
WA
LP3
LP2
LP1
LP0 0000 0000 64, 259
Legend:
Note 1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 64-pin devices; read as ‘0’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
The RG5 bit is only available when Master Clear is disabled (MCLRE configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
These registers are implemented but unused in 64-pin devices and may be used as general-purpose data RAM if required.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 79