PIC18F6390 Datasheet, PDF (406/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
OSCCON (Oscillator Control) .................................... 38
OSCTUNE (Oscillator Tuning) ................................... 35
PIE1 (Peripheral Interrupt Enable 1) ........................ 101
PIE2 (Peripheral Interrupt Enable 2) ........................ 102
PIE3 (Peripheral Interrupt Enable 3) ........................ 103
PIR1 (Peripheral Interrupt
Request (Flag) 1) ............................................... 98
PIR2 (Peripheral Interrupt
Request (Flag) 2) ............................................... 99
PIR3 (Peripheral Interrupt
Request (Flag) 3) ............................................. 100
RCON (Reset Control) ....................................... 52, 107
RCSTA1 (EUSART Receive Status
and Control) ..................................................... 199
RCSTA2 (AUSART Receive Status
and Control) ..................................................... 219
SSPCON1 (MSSP Control 1, I²C Mode) ................. 168
SSPCON1 (MSSP Control 1, SPI Mode) ................. 159
SSPCON2 (MSSP Control 2, I²C Mode) ................. 169
SSPSTAT (MSSP Status, I²C Mode) ....................... 167
SSPSTAT (MSSP Status, SPI Mode) ...................... 158
Status ......................................................................... 80
STKPTR (Stack Pointer) ............................................ 67
T0CON (Timer0 Control) .......................................... 131
T1CON (Timer1 Control) .......................................... 135
T2CON (Timer 2 Control) ......................................... 141
T3CON (Timer3 Control) .......................................... 143
TXSTA1 (EUSART Transmit Status
and Control) ..................................................... 198
TXSTA2 (AUSART Transmit Status
and Control) ..................................................... 218
WDTCON (Watchdog Timer Control) ....................... 288
RESET ............................................................................. 325
Reset .................................................................................. 51
MCLR Reset, during Power
Managed Modes ................................................ 51
MCLR Reset, Normal Operation ................................ 51
Power-on Reset (POR) .............................................. 51
Programmable Brown-out
Reset (BOR) ...................................................... 51
Stack Full Reset ......................................................... 51
Stack Underflow Reset .............................................. 51
Watchdog Timer (WDT) Reset ................................... 51
Resets .............................................................................. 281
RETFIE ............................................................................ 326
RETLW ............................................................................. 326
RETURN .......................................................................... 327
Return Address Stack ........................................................ 66
Return Stack Pointer (STKPTR) ........................................ 67
Revision History ............................................................... 393
RLCF ................................................................................ 327
RLNCF ............................................................................. 328
RRCF ............................................................................... 328
RRNCF ............................................................................. 329
S
SCK .................................................................................. 157
SDI ................................................................................... 157
SDO ................................................................................. 157
Serial Clock, SCK ............................................................. 157
Serial Data In (SDI) .......................................................... 157
Serial Data Out (SDO) ..................................................... 157
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 329
Slave Select (SS) ............................................................. 157
SLEEP ............................................................................. 330
Sleep
OSC1 and OSC2 Pin States ...................................... 39
Software Enabled BOR ...................................................... 54
Software Simulator (MPLAB SIM) ................................... 346
Software Simulator (MPLAB SIM30) ............................... 346
Special Event Trigger.
See Compare (CCP Module).
Special Features of the CPU ........................................... 281
Special Function Registers ................................................ 74
Map ...................................................................... 74–75
SPI Mode (MSSP)
Associated Registers ............................................... 165
Bus Mode Compatibility ........................................... 165
Effects of a Reset .................................................... 165
Enabling SPI I/O ...................................................... 161
Master Mode ............................................................ 162
Master/Slave Connection ......................................... 161
Operation ................................................................. 160
Serial Clock .............................................................. 157
Serial Data In ........................................................... 157
Serial Data Out ........................................................ 157
Slave Mode .............................................................. 163
Slave Select ............................................................. 157
Slave Select Synchronization .................................. 163
Sleep Operation ....................................................... 165
SPI Clock ................................................................. 162
Typical Connection .................................................. 161
SS .................................................................................... 157
SSPOV ............................................................................ 187
SSPOV Status Flag ......................................................... 187
SSPSTAT Register
R/W Bit ............................................................ 170, 171
Stack Full/Underflow Resets .............................................. 68
Status Register .................................................................. 80
SUBFSR .......................................................................... 341
SUBFWB ......................................................................... 330
SUBLW ............................................................................ 331
SUBULNK ........................................................................ 341
SUBWF ............................................................................ 331
SUBWFB ......................................................................... 332
SWAPF ............................................................................ 332
T
Table Pointer Operations (table) ........................................ 88
Table Reads ...................................................................... 68
TBLRD ............................................................................. 333
TBLWT ............................................................................. 334
Time-out in Various Situations (table) ................................ 55
Timer0 .............................................................................. 131
16-Bit Mode Timer Reads
and Writes ....................................................... 132
Associated Registers ............................................... 133
Clock Source Edge Select
(T0SE Bit) ........................................................ 132
Clock Source Select (T0CS Bit) ............................... 132
Operation ................................................................. 132
Overflow Interrupt .................................................... 133
Prescaler. See Prescaler, Timer0.
DS39629B-page 404
Preliminary
 2004 Microchip Technology Inc.