PIC18F6390 Datasheet, PDF (76/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
5.3.4 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
three-quarters of Bank 15 (from F40h to FFFh). A list of
these registers is given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The reset and interrupt registers
are described in their respective chapters, while the
ALU’s Status register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F6390/6490/8390/8490 DEVICES
Address
Name
FFFh
TOSU
FFEh
TOSH
FFDh
TOSL
FFCh STKPTR
FFBh PCLATU
FFAh PCLATH
FF9h
PCL
FF8h TBLPTRU
FF7h TBLPTRH
FF6h TBLPTRL
FF5h TABLAT
FF4h PRODH
FF3h PRODL
FF2h INTCON
FF1h INTCON2
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
INTCON3
INDF0⁽¹⁾
POSTINC0⁽¹⁾
POSTDEC0⁽¹⁾
PREINC0⁽¹⁾
PLUSW0⁽¹⁾
FEAh FSR0H
FE9h FSR0L
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
WREG
INDF1⁽¹⁾
POSTINC1⁽¹⁾
POSTDEC1⁽¹⁾
PREINC1⁽¹⁾
PLUSW1⁽¹⁾
FE2h FSR1H
FE1h FSR1L
FE0h
BSR
Address
Name
FDFh
FDEh
FDDh
FDCh
FDBh
INDF2⁽¹⁾
POSTINC2⁽¹⁾
POSTDEC2⁽¹⁾
PREINC2⁽¹⁾
PLUSW2⁽¹⁾
FDAh FSR2H
FD9h FSR2L
FD8h STATUS
FD7h TMR0H
FD6h TMR0L
FD5h
FD4h
T0CON
—⁽²⁾
FD3h OSCCON
FD2h HLVDCON
FD1h WDTCON
FD0h
RCON
FCFh TMR1H
FCEh TMR1L
FCDh T1CON
FCCh
TMR2
FCBh
PR2
FCAh T2CON
FC9h SSPBUF
FC8h SSPADD
FC7h SSPSTAT
FC6h SSPCON1
FC5h SSPCON2
FC4h ADRESH
FC3h ADRESL
FC2h ADCON0
FC1h ADCON1
FC0h ADCON2
Address
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
Name
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
—⁽²⁾
—⁽²⁾
—⁽²⁾
—⁽²⁾
CVRCON
CMCON
TMR3H
TMR3L
T3CON
—⁽²⁾
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
—⁽²⁾
—⁽²⁾
—⁽²⁾
—⁽²⁾
—⁽²⁾
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
Note 1:
2:
3:
4:
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is not available on 64-pin devices.
This register is implemented but unused on 64-pin devices.
Address
Name
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
IPR1
PIR1
PIE1
MEMCON⁽³⁾
OSCTUNE
TRISJ⁽³⁾
TRISH⁽³⁾
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ⁽³⁾
LATH⁽³⁾
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTJ⁽³⁾
PORTH⁽³⁾
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
DS39629B-page 74
Preliminary
 2004 Microchip Technology Inc.