PIC18F6390 Datasheet, PDF (127/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
9.7 PORTG, TRISG and
LATG Registers
PORTG is a 6-bit wide, bidirectional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTG pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register read and write the latched output value for
PORTG.
PORTG is multiplexed with both USART and LCD
functions (Table 9-14). PORTG pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings. The pin override value is not loaded into
the TRIS register. This allows read-modify-write of the
TRIS register without concern due to peripheral
overrides.
PORTG<4:0> are also multiplexed with LCD segment
drives controlled by bits in the LCDSE3 register. I/O
port functions are only available when the segments
are disabled.
The sixth pin of PORTG (MCLR/VPP/RG5) is an input
only pin. Its operation is controlled by the MCLRE
configuration bit. When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RG5 also
functions as the programming voltage input during
programming.
Note:
On a Power-on Reset, RG5 is enabled as
a digital input only if Master Clear
functionality is disabled. All other 5 pins
are configured as digital inputs.
EXAMPLE 9-7: INITIALIZING PORTG
CLRF
CLRF
MOVLW
MOVWF
PORTG
LATG
0x04
TRISG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 125