PIC18F6390 Datasheet, PDF (146/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
13.1 Timer3 Operation
Timer3 can operate in one of three modes:
• Timer
• Synchronous counter
• Asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (FOSC/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
As with Timer1, the RC1/T1OSI and
RC0/T1OSO/T13CKI pins become inputs when the
Timer1 oscillator is enabled. This means the values of
TRISC<1:0> are ignored and the pins are read as ‘0’.
FIGURE 13-1:
T1OSO/T13CKI
T1OSI
TIMER3 BLOCK DIAGRAM
Timer1 Oscillator
1
FOSC/4
Internal
Clock
0
T1OSCEN⁽¹⁾
TMR3CS
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
Prescaler
1, 2, 4, 8
2
1
Synchronize
Detect
0
Sleep Input
Timer3
On/Off
CCP Special Event Trigger
TCCPx
Clear TMR3
TMR3L
TMR3
High Byte
Note 1: When T1OSCEN is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Set
TMR3IF
on Overflow
FIGURE 13-2:
T1OSO/T13CKI
T1OSI
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
Timer1 Clock Input
1
1
FOSC/4
Internal
Clock
0
T1OSCEN⁽¹⁾
TMR3CS
T3CKPS1:T3CKPS0
T3SYNC
TMR3ON
Prescaler
1, 2, 4, 8
2
Synchronize
Detect
0
Sleep Input
Timer3
On/Off
CCP Special Event Trigger
TCCPx
Clear TMR3
TMR3L
TMR3
High Byte
8
Set
TMR3IF
on Overflow
Read TMR3L
8
8
Write TMR3L
TMR3H
8
8
Note 1: When T1OSCEN is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Internal Data Bus
DS39629B-page 144
Preliminary
 2004 Microchip Technology Inc.