PIC18F6390 Datasheet, PDF (149/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
14.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
PIC18F6390/6490/8390/8490 devices have two CCP
(Capture/Compare/PWM) modules, designated CCP1
and CCP2. Both modules implement standard Capture,
Compare and Pulse Width Modulation (PWM) modes.
Each CCP module contains a 16-bit register which can
operate as a 16-bit Capture register, a 16-bit Compare
register or a PWM Master/Slave Duty Cycle register.
For the sake of clarity, all CCP module operation in the
following sections is described with respect to CCP2,
but is equally applicable to CCP1.
REGISTER 14-1:
CCPxCON REGISTER (CCP1 MODULE, CCP2 MODULE)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
DCxB1 DCxB0 CCPxM3 CCPxM2
bit 7
R/W-0 R/W-0
CCPxM1 CCPxM0
bit 0
bit 7-6
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM Duty Cycle. The
eight Most Significant bits (DCx9:DCx2) of the Duty Cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode: initialize CCP pin low; on compare match, force CCP pin high
(CCPIF bit is set)
1001 = Compare mode: initialize CCP pin high; on compare match, force CCP pin low
(CCPIF bit is set)
1010 = Compare mode: generate software interrupt on compare match (CCPIF bit is set,
CCP pin reflects I/O state)
1011 = Compare mode: trigger special event, reset timer, start A/D conversion on
CCP2 match (CCPIF bit is set)⁽¹⁾
11xx = PWM mode
Note 1: CCP1M3:CCP1M0 = 1011 will only reset timer and not start A/D conversion on
CCP1 match.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 147