PIC18F6390 Datasheet, PDF (43/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
3.0 POWER MANAGED MODES
PIC18F6390/6490/8390/8490 devices offer a total of
seven operating modes for more efficient power
management. These modes provide a variety of
options for selective power conservation in applications
where resources may be limited (i.e., battery-powered
devices).
There are three categories of power managed modes:
• Sleep mode
• Idle modes
• Run modes
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The power managed modes include several power
saving features. One of these is the clock switching
feature, offered in other PIC18 devices, allowing the
controller to use the Timer1 oscillator in place of the
primary oscillator. Also included is the Sleep mode,
offered by all PICmicro^® devices, where all device
clocks are stopped.
3.1 Selecting Power Managed Modes
Selecting a power managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit controls CPU clocking, while the
SCS1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
3.1.1 CLOCK SOURCES
The SCS1:SCS0 bits allow the selection of one of three
clock sources for power managed modes. They are:
• the primary clock, as defined by the
FOSC3:FOSC0 configuration bits
• the secondary clock (the Timer1 oscillator)
• the internal oscillator block (for RC modes)
3.1.2
ENTERING POWER MANAGED
MODES
Entering Power Managed Run mode, or switching from
one power managed mode to another, begins by
loading the OSCCON register. The SCS1:SCS0 bits
select the clock source and determine which Run or
Idle mode is being used. Changing these bits causes
an immediate switch to the new clock source,
assuming that it is running. The switch may also be
subject to clock transition delays. These are discussed
in Section 3.1.3 “Clock Transitions and Status
Indicators” and subsequent sections.
Entry to the Power Managed Idle or Sleep modes is
triggered by the execution of a SLEEP instruction. The
actual mode that results depends on the status of the
IDLEN bit.
Depending on the current mode and the mode being
switched to, a change to a power managed mode does
not always require setting all of these bits. Many transi-
tions may be done by changing the oscillator select
bits, or changing the IDLEN bit prior to issuing a SLEEP
instruction. If the IDLEN bit is already configured
correctly, it may only be necessary to perform a SLEEP
instruction to switch to the desired mode.
TABLE 3-1: POWER MANAGED MODES
Mode
OSCCON bits
IDLEN⁽¹⁾ SCS1:SCS0
<7>
<1:0>
Module Clocking
CPU Peripherals
Available Clock and Oscillator Source
Sleep
0
PRI_RUN
N/A
N/A
Off
Off None – All clocks are disabled
00
Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC⁽²⁾:
This is the normal full power execution mode.
SEC_RUN
N/A
RC_RUN
N/A
01
Clocked Clocked Secondary – Timer1 Oscillator
1x
Clocked Clocked Internal Oscillator Block⁽²⁾
PRI_IDLE
1
00
Off
Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE
1
RC_IDLE
1
01
Off
Clocked Secondary – Timer1 Oscillator
1x
Off
Clocked Internal Oscillator Block⁽²⁾
Note 1: IDLEN reflects its value when the SLEEP instruction is executed.
2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 41