PIC18F6390 Datasheet, PDF (211/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
FIGURE 16-7:
RX1 (pin)
Rcv Shift Reg
Rcv Buffer Reg
RCREG1
Read Rcv
Buffer Reg
RC1IF
(Interrupt Flag)
OERR bit
CREN bit
ASYNCHRONOUS RECEPTION
Start
bit _{bit 0 bit 1}
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREG1
Start
bit 7/8 Stop bit
bit
Word 2
RCREG1
bit 7/8 Stop
bit
Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word
causing the OERR (Overrun) bit to be set.
TABLE 16-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR1
—
ADIF
RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF
61
PIE1
—
ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 61
IPR1
—
ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 61
RCSTA1
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
61
RCREG1 EUSART1 Receive Register
61
TXSTA1
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
61
BAUDCON1 ABDOVF RCIDL
—
SCKP BRG16
—
WUE ABDEN
62
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte
62
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte
61
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 209