PIC18F6390 Datasheet, PDF (47/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
3.3 Sleep Mode
The Power Managed Sleep mode in the
PIC18F6390/6490/8390/8490 devices is identical to
the Legacy Sleep mode offered in all other PICmicro
devices. It is entered by clearing the IDLEN bit (the
default state on device Reset) and executing the
SLEEP instruction. This shuts down the selected
oscillator (see Figure 3-5). All clock source status bits
are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the primary clock source becomes ready (see
Figure 3-6), or it will be clocked from the internal oscil-
lator block if either the Two-Speed Start-up or the
Fail-Safe Clock Monitor are enabled (see Section 23.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock provides the
device clocks. The IDLEN and SCS bits are not
affected by the wake-up.
3.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction
is executed, the peripherals will be clocked from the
clock source selected using the SCS1:SCS0 bits;
however, the CPU will not be clocked. The clock source
status bits are not affected. Setting IDLEN and execut-
ing SLEEP provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 26-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
FIGURE 3-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 3-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
PLL Clock
Output
TOST⁽¹⁾
TPLL⁽¹⁾
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
Wake Event
OSTS bit set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PC + 4
PC + 6
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 45