PIC18F6390 Datasheet, PDF (242/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
18.8 Use of the CCP2 Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the “special event trigger”
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TABLE 18-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
59
PIR1
—
ADIF
RC1IF
TX1IF
SSPIF CCP1IF TMR2IF TMR1IF
61
PIE1
—
ADIE
RC1IE
TX1IE
SSPIE CCP1IE TMR2IE TMR1IE
61
IPR1
—
ADIP
RC1IP
TX1IP
SSPIP CCP1IP TMR2IP TMR1IP
61
PIR2
OSCFIF CMIF
—
—
BCLIF HLVDIF TMR3IF CCP2IF
61
PIE2
OSCFIE CMIE
—
—
BCLIE HLVDIE TMR3IE CCP2IE
61
IPR2
OSCFIP CMIP
—
—
BCLIP HLVDIP TMR3IP CCP2IP
61
ADRESH A/D Result Register High Byte
61
ADRESL A/D Result Register Low Byte
61
ADCON0
—
—
CHS3
CHS2
CHS1 CHS0 GO/DONE ADON
61
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
61
ADCON2 ADFM
—
ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
61
PORTA
RA7⁽¹⁾
RA6⁽¹⁾
RA5
RA4
RA3
RA2
RA1
RA0
62
TRISA
TRISA7⁽¹⁾ TRISA6⁽¹⁾ PORTA Data Direction Register
62
PORTF Read PORTF pins, Write LATF Latch
62
TRISF PORTF Data Direction Register
62
LATF
PORTF Output Data Latch
62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: These pins may be configured as port pins depending on the oscillator mode selected.
DS39629B-page 240
Preliminary
 2004 Microchip Technology Inc.