PIC18F6390 Datasheet, PDF (120/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
9.4 PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register read and write the latched output value for
PORTD.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
PORTD is also multiplexed with LCD segment drives
controlled by the LCDSE0 register. I/O port functions
are only available when the segments are disabled.
EXAMPLE 9-4: INITIALIZING PORTD
CLRF
CLRF
MOVLW
MOVWF
PORTD
LATD
0CFh
TRISD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
TABLE 9-7: PORTD FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
Buffer
Description
RD0/SEG0
RD0
0
O
DIG LATD<0> data output; disabled when LCD segment enabled.
1
I
ST PORTD<0> data input.
SEG0
x
O
ANA Segment 0 analog output for LCD.
RD1/SEG1
RD1
0
O
DIG LATD<1> data output; disabled when LCD segment enabled.
1
I
ST PORTD<1> data input.
SEG1
x
O
ANA Segment 1 analog output for LCD.
RD2/SEG2
RD2
0
O
DIG LATD<2> data output; disabled when LCD segment enabled.
1
I
ST PORTD<2> data input.
SEG2
x
O
ANA Segment 2 analog output for LCD.
RD3/SEG3
RD3
0
O
DIG LATD<3> data output; disabled when LCD segment enabled.
1
I
ST PORTD<3> data input.
SEG3
x
O
ANA Segment 3 analog output for LCD.
RD4/SEG4
RD4
0
O
DIG LATD<4> data output; disabled when LCD segment enabled.
1
I
ST PORTD<4> data input.
SEG4
x
O
ANA Segment 4 analog output for LCD module.
RD5/SEG5
RD5
0
O
DIG LATD<5> data output; disabled when LCD segment enabled.
1
I
ST PORTD<5> data input.
SEG5
x
O
ANA Segment 5 analog output for LCD.
RD6/SEG6
RD6
0
O
DIG LATD<6> data output; disabled when LCD segment enabled.
1
I
ST PORTD<6> data input.
SEG6
x
O
ANA Segment 6 analog output for LCD.
RD7/SEG7
RD7
0
O
DIG LATD<7> data output; disabled when LCD segment enabled.
1
I
ST PORTD<7> data input.
SEG7
x
O
ANA Segment 7 analog output for LCD.
Legend: PWR - Power Supply, O - Output, I - Input, ANA - Analog Signal, DIG - Digital Output, ST - Schmitt Buffer Input,
TTL - TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
DS39629B-page 118
Preliminary
 2004 Microchip Technology Inc.