PIC18F6390 Datasheet, PDF (46/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
3.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive, or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator block
(either INTRC or INTOSC), there are no distinguishable
differences between PRI_RUN and RC_RUN modes
during execution. However, a clock switch delay will occur
during entry to and exit from RC_RUN mode. Therefore,
if the primary clock source is the internal oscillator block,
the use of RC_RUN mode is not recommended.
This mode is entered by setting the SCS1 bit to ‘1’.
Although it is ignored, it is recommended that the SCS0
bit also be cleared; this is to maintain software
compatibility with future devices. When the clock
source is switched to the INTOSC multiplexer (see
Figure 3-3), the primary oscillator is shut down and the
OSTS bit is cleared.The IRCF bits may be modified at
any time to immediately change the clock speed.
Note:
Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source provides the device
clocks.
If the IRCF bits are changed from all clear (thus
enabling the INTOSC output), or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
TIOBST.
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
On transitions from RC_RUN mode to PRI_RUN, the
device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock provides the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-3:
INTRC
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
123
n-1 n
Clock Transition
PC
PC + 2
Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
FIGURE 3-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
INTOSC
Multiplexer
Q1
Q2
Q3
Q4 Q1
Q2 Q3 Q4 Q1 Q2 Q3
OSC1
PLL Clock
Output
CPU Clock
TOST⁽¹⁾
TPLL⁽¹⁾
1 2 n-1 n
Clock
Transition
Peripheral
Clock
Program
Counter
PC
PC + 2
SCS1:SCS0 bits changed
OSTS bit set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PC + 4
DS39629B-page 44
Preliminary
 2004 Microchip Technology Inc.