PIC18F6390 Datasheet, PDF (283/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
23.0 SPECIAL FEATURES
OF THE CPU
PIC18F6390/6490/8390/8490 devices include several
features intended to maximize reliability and minimize
cost through elimination of external components.
These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 2.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator start-up
timers provided for Resets, PIC18F6390/6490/8390/
8490 devices have a Watchdog Timer, which is either
permanently enabled via the configuration bits, or
software controlled (if configured as disabled).
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate configuration register bits.
23.1 Configuration Bits
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh),
which can only be accessed using table reads.
TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs
File Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
300001h CONFIG1H IESO FCMEN —
—
FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111
300002h CONFIG2L —
—
—
BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111
300003h CONFIG2H —
—
— WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE —
—
—
— LPT1OSC —
CCP2MX 1--- -0-1
300006h CONFIG4L DEBUG XINST
—
—
—
—
—
STVREN 10-- ---1
300008h CONFIG5L
3FFFFEh DEVID1
3FFFFFh DEVID2
—
DEV2
DEV10
—
DEV1
DEV9
—
DEV0
DEV8
—
REV4
DEV7
—
REV3
DEV6
—
REV2
DEV5
—
REV1
DEV4
CP
REV0
DEV3
---- ---1
xxxx xxxx⁽¹⁾
0000 xxxx⁽¹⁾
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’.
See Register 23-7 for DEVID values. DEVID registers are read-only and cannot be programmed by the user.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 281