PIC18F6390 Datasheet, PDF (128/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
TABLE 9-14: PORTG FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
Buffer
Description
RG0/SEG30
RG0
0
O
DIG LATG<0> data output; disabled when LCD segment enabled.
1
I
ST PORTG<0> data input.
SEG30
x
O
ANA Segment 30 analog output for LCD.
RG1/TX2/CK2/
RG1
0
O
DIG LATG<1> data output; disabled when LCD segment enabled.
SEG29
1
I
ST PORTG<1> data input.
TX2
1
O
DIG Synchronous serial data output (AUSART module); takes priority over
port data.
CK2
1
O
DIG Synchronous serial data input (AUSART module). User must configure
as an input.
1
I
ST Synchronous serial clock input (AUSART module).
SEG29
x
O
ANA Segment 29 analog output for LCD.
RG2/RX2/DT2/
RG2
0
O
DIG LATG<2> data output; disabled when LCD segment enabled.
SEG28
1
I
ST PORTG<2> data input.
RX2
1
I
ST Asynchronous serial receive data input (AUSART module).
DT2
1
O
DIG Synchronous serial data output (AUSART module); takes priority over
port data.
1
I
ST Synchronous serial data input (AUSART module). User must configure
as an input.
SEG28
x
O
ANA Segment 28 analog output for LCD.
RG3/SEG27
RG3
0
O
DIG LATG<3> data output; disabled when LCD segment enabled.
1
I
ST PORTG<3> data input.
SEG27
0
O
ANA Segment 27 analog output for LCD.
RG4/SEG26
RG4
0
O
DIG LATG<4> data output; disabled when LCD segment enabled.
1
I
ST PORTG<4> data input.
MCLR/VPP/RG5
SEG26
MCLR
VPP
RG5
x
—⁽¹⁾
—⁽¹⁾
—⁽¹⁾
O
ANA Segment 26 analog output for LCD.
I
ST External Master Clear input; enabled when MCLRE configuration bit is set.
I
ANA High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
I
ST PORTG<5> data input; enabled when MCLRE configuration bit is clear.
Legend:
Note 1:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RG5 does not have a corresponding TRISG bit.
TABLE 9-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
PORTG
—
—
RG5⁽¹⁾ Read PORTG pin/Write PORTG Data Latch
LATG
—
—
— LATG Data Output Register
TRISG
—
—
— Data Direction Control Register for PORTG
LCDSE3
SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.
Note 1: RG5 is available as an input only when MCLR is disabled.
Reset Values
on Page
62
62
62
64
DS39629B-page 126
Preliminary
 2004 Microchip Technology Inc.