PIC18F6390 Datasheet, PDF (381/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
FIGURE 26-14:
SS
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1)
82
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
bit 6 - - - - - - 1
LSb
75, 76
77
SDI
MSb In
bit 6 - - - - 1
LSb In
74
Note: Refer to Figure 26-4 for load conditions.
TABLE 26-16: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70 TSSL2SCH, SS↓ to SCK↓ or SCK↑ Input
TSSL2SCL
TCY
—
71 TSCH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72 TSCL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
—
75 TDOR
SDO Data Output Rise Time
PIC18FXXXX
—
25
PIC18LFXXXX
—
45
76 TDOF
SDO Data Output Fall Time
—
25
77 TSSH2DOZ SS↑ to SDO Output High-Impedance
10
50
78 TSCR
SCK Output Rise Time
(Master mode)
PIC18FXXXX
PIC18LFXXXX
—
25
—
45
79 TSCF
SCK Output Fall Time (Master mode)
—
25
80 TSCH2DOV, SDO Data Output Valid after SCK PIC18FXXXX
TSCL2DOV Edge
PIC18LFXXXX
—
50
—
100
82 TSSL2DOV SDO Data Output Valid after SS↓ PIC18FXXXX
Edge
PIC18LFXXXX
—
50
—
100
83 TSCH2SSH, SS ↑ after SCK Edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
ns VDD = 2.0V
ns
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 379