PIC18F6390 Datasheet, PDF (289/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
23.2 Watchdog Timer (WDT)
For PIC18F6390/6490/8390/8490 devices, the WDT is
driven by the INTRC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 134.2 seconds (2.24 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits (OSCCON<6:4>) are changed, or a clock
failure has occurred.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits
(OSCCON<6:4>) clears the WDT and
postscaler counts.
3: When a CLRWDT instruction is executed
the postscaler count will be cleared.
23.2.1 CONTROL REGISTER
Register 23-9 shows the WDTCON register. This is a
readable and writable register, which contains a control
bit that allows software to override the WDT enable
configuration bit, but only if the configuration bit has
disabled the WDT.
FIGURE 23-1:
WDT BLOCK DIAGRAM
SWDTEN
WDTEN
INTRC Source
Change on IRCF bits
CLRWDT
All Device Resets
WDTPS<3:0>
Sleep
Enable WDT
INTRC Control
WDT Counter
÷128
Programmable Postscaler ^Reset
1:1 to 1:32,768
WDT
4
Wake-up
from Power
Managed Modes
WDT
Reset
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 287