PIC18F6390 Datasheet, PDF (51/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up
Exit Delay
Clock Ready Status
Bit (OSCCON)
Primary Device Clock
(PRI_IDLE mode)
T1OSC or INTRC⁽¹⁾
INTOSC⁽³⁾
None
(Sleep mode)
LP, XT, HS
HSPLL
EC, RC, INTRC⁽¹⁾
INTOSC⁽³⁾
LP, XT, HS
HSPLL
EC, RC, INTRC⁽¹⁾
INTOSC⁽²⁾
LP, XT, HS
HSPLL
EC, RC, INTRC⁽¹⁾
INTOSC⁽²⁾
LP, XT, HS
HSPLL
EC, RC, INTRC⁽¹⁾
INTOSC⁽²⁾
TCSD⁽²⁾
TOST⁽⁴⁾
TOST + t_rc⁽⁴⁾
TCSD⁽²⁾
TIOBST⁽⁵⁾
TOST⁽⁵⁾
TOST + t_rc⁽⁴⁾
TCSD⁽²⁾
None
TOST⁽⁴⁾
TOST + t_rc⁽⁴⁾
TCSD⁽²⁾
TIOBST⁽⁵⁾
OSTS
—
IOFS
OSTS
—
IOFS
OSTS
—
IOFS
OSTS
—
IOFS
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
with any other required delays (see Section 3.4 “Idle Modes”).
3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
4: TOST is the Oscillator Start-up Timer (parameter 32). t_rc is the PLL Lock-out Timer (parameter F12); it is
also designated as TPLL.
5: Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 49