PIC18F6390 Datasheet, PDF (185/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
15.4.7 BAUD RATE
In I²C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 15-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I²C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 15-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
CLKO
BRG Down Counter
FOSC/4
TABLE 15-3: I²C™ CLOCK RATE W/BRG
FCY
FCY*2
BRG Value
FSCL
(2 Rollovers of BRG)
10 MHz
20 MHz
19h
400 kHz⁽¹⁾
10 MHz
20 MHz
20h
312.5 kHz
10 MHz
4 MHz
20 MHz
8 MHz
3Fh
100 kHz
0Ah
400 kHz⁽¹⁾
4 MHz
8 MHz
0Dh
308 kHz
4 MHz
1 MHz
8 MHz
2 MHz
28h
100 kHz
03h
333 kHz⁽¹⁾
Note 1:
1 MHz
2 MHz
0Ah
100 kHz
1 MHz
2 MHz
00h
1 MHz⁽¹⁾
The I²C interface does not conform to the 400 kHz I²C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 183