PIC18F6390 Datasheet, PDF (48/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
3.4.1 PRI_IDLE MODE
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 configuration bits. The OSTS bit
remains set (see Figure 3-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).
FIGURE 3-7:
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
TRANSITION TIMING FOR ENTRY TO PRI_IDLE MODE
Q1
Q2
Q3
Q4
Q1
PC
PC + 2
FIGURE 3-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
TCSD
Q2
Q3
Q4
PC
Wake Event
DS39629B-page 46
Preliminary
 2004 Microchip Technology Inc.