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PIC18F6390 Datasheet, PDF (385/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology | |||
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PIC18F6390/6490/8390/8490
TABLE 26-20: MASTER SSP I2C⢠BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) â ms
400 kHz mode 2(TOSC)(BRG + 1) â ms
1 MHz mode(1) 2(TOSC)(BRG + 1) â
ms
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) â ms
400 kHz mode 2(TOSC)(BRG + 1) â ms
1 MHz mode(1) 2(TOSC)(BRG + 1) â
ms
102 TR
SDA and SCL
Rise Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
â
20 + 0.1 CB
â
1000
300
300
ns CB is specified to be from
ns 10 to 400 pF
ns
103 TF
SDA and SCL
Fall Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
â
20 + 0.1 CB
â
300 ns CB is specified to be from
300 ns 10 to 400 pF
100 ns
90
TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) â ms Only relevant for
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) â
1 MHz mode(1) 2(TOSC)(BRG + 1) â
ms Repeated Start
condition
ms
91
THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) â ms After this period, the first
Hold Time
400 kHz mode 2(TOSC)(BRG + 1) â
ms clock pulse is generated
1 MHz mode(1) 2(TOSC)(BRG + 1) â
ms
106 THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
0
0
TBD
â
ns
0.9 ms
â
ns
107 TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
250
100
TBD
â
ns (Note 2)
â
ns
â
ns
92
TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) â ms
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) â ms
1 MHz mode(1) 2(TOSC)(BRG + 1) â
ms
109 TAA
Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
â
3500 ns
â
1000 ns
â
â
ns
110 TBUF Bus Free Time 100 kHz mode
400 kHz mode
1 MHz mode(1)
4.7
1.3
TBD
â ms Time the bus must be free
â
ms before a new transmission
can start
â ms
D102 CB
Bus Capacitive Loading
â
400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C⢠pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ⥠250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode,) before the
SCL line is released.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 383
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