PIC18F6390 Datasheet, PDF (265/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
22.3 LCD Bias Types
The LCD driver module can be configured into three
bias types:
• Static Bias (2 voltage levels: AVSS and AVDD)
• 1/2 Bias (3 voltage levels: AVSS, 1/2 AVDD and
AVDD)
• 1/3 Bias (4 voltage levels: AVSS, 1/3 AVDD, 2/3 AVDD
and AVDD)
This module uses an external resistor ladder to
generate the LCD bias voltages.
The external resistor ladder should be connected to the
Bias 1 pin, Bias 2 pin, Bias 3 pin and VSS. The Bias 1
pin should also be connected to VDD.
Figure 22-3 shows the proper way to connect the
resistor ladder to the Bias pins.
22.4 LCD Multiplex Types
The LCD driver module can be configured into four
multiplex types:
• Static (only COM0 used)
• 1/2 multiplex (COM0 and COM1 are used)
• 1/3 multiplex (COM0, COM1 and COM2 are used)
• 1/4 multiplex (all COM0, COM1, COM2 and COM3
are used)
The LMUX1:LMUX0 setting decides the function of the
PORTE<6:4> bits (see Table 22-3 for details).
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. If the pin is a COM drive,
then the TRIS setting of that pin is overridden.
Note: On a Power-on Reset, the LMUX1:LMUX0
bits are ‘00’.
TABLE 22-3: PORTE<6:4> FUNCTION
LMUX1:
LMUX0
PORTE<6>
PORTE<5>
PORTE<4>
00
Digital I/O Digital I/O Digital I/O
01
Digital I/O Digital I/O COM1 Driver
10
Digital I/O COM2 Driver COM1 Driver
11 COM3 Driver COM2 Driver COM1 Driver
22.5 Segment Enables
The LCDSEx registers are used to select the pin
function for each segment pin. The selection allows
each pin to operate as either an LCD segment driver or
a digital only pin. To configure the pin as a segment pin,
the corresponding bits in the LCDSEx registers must
be set to ‘1’.
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. Any bit set in the LCDSEx
registers overrides any bit settings in the corresponding
TRIS register.
Note: On a Power-on Reset, these pins are
configured as digital I/O.
FIGURE 22-3:
LCD BIAS RESISTOR LADDER CONNECTION DIAGRAM
VLCD 3
VLCD 2
VLCD 1
VLCD 0
To
LCD
Driver
VLCD 0
VLCD 1
VLCD 2
VLCD 3
Static
Bias
AVSS
—
—
AVDD
1/2 Bias 1/3 Bias
AVSS
AVSS
1/2 AVDD 1/3 AVDD
1/2 AVDD 2/3 AVDD
AVDD
AVDD
AVDD*
LCD Bias 3 LCD Bias 2 LCD Bias 1
AVDD*
10 kΩ*
10 kΩ*
AVDD*
10 kΩ*
10 kΩ*
10 kΩ*
Connections for External R-ladder
Static Bias
AVSS
1/2 Bias
AVSS
1/3 Bias
* These values are provided for design guidance only and should be optimized for the application by the designer.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 263