PIC18F6390 Datasheet, PDF (231/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
17.4 AUSART Synchronous Slave Mode
Synchronous Slave mode is entered by clearing bit
CSRC (TXSTA2<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK2 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
low-power mode.
17.4.1 AUSART SYNCHRONOUS
SLAVE TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG2 and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG2
register.
c) Flag bit TX2IF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG2 register will transfer the second
word to the TSR and flag bit TX2IF will now be
set.
e) If enable bit TX2IE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TX2IE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG2 register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 17-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR3
—
LCDIF RC2IF TX2IF
—
—
—
—
61
PIE3
—
LCDIE RC2IE TX2IE
—
—
—
—
61
IPR3
—
LCDIP RC2IP TX2IP
—
—
—
—
61
RCSTA2
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
63
TXREG2 AUSART2 Transmit Register
63
TXSTA2
CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D
63
SPBRG2 AUSART2 Baud Rate Generator Register Low Byte
63
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 229