PIC18F6390 Datasheet, PDF (222/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
17.1 AUSART Baud Rate Generator
(BRG)
The BRG is a dedicated 8-bit generator that supports
both the Asynchronous and Synchronous modes of the
AUSART.
The SPBRG2 register controls the period of a free
running timer. In Asynchronous mode, bit BRGH
(TXSTA<2>) also controls the baud rate. In Synchro-
nous mode, BRGH is ignored. Table 17-1 shows the
formula for computation of the baud rate for different
AUSART modes, which only apply in Master mode
(internally generated clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG2 register can be calcu-
lated using the formulas in Table 17-1. From this, the
error in baud rate can be determined. An example
calculation is shown in Example 17-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 17-2. It may be advanta-
geous to use the high baud rate (BRGH = 1) to reduce
the baud rate error, or achieve a slow baud rate for a
fast oscillator frequency.
Writing a new value to the SPBRG2 register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting
the new baud rate.
17.1.1 OPERATION IN POWER MANAGED
MODES
The device clock is used to generate the desired baud
rate. When one of the power managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG2 register.
17.1.2 SAMPLING
The data on the RX2 pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX2 pin.
TABLE 17-1: BAUD RATE FORMULAS
Configuration Bits
SYNC
BRGH
BRG/AUSART Mode
0
0
Asynchronous
0
1
Asynchronous
1
x
Synchronous
Legend: x = Don’t care, n = Value of SPBRG2 register
Baud Rate Formula
FOSC/[64 (n + 1)]
FOSC/[16 (n + 1)]
FOSC/[4 (n + 1)]
EXAMPLE 17-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:
Desired Baud Rate = FOSC/(64 ([SPBRG2] + 1))
Solving for SPBRG2:
X = ((FOSC/Desired Baud Rate)/64) – 1
= ((16000000/9600)/64) – 1
= [25.042] = 25
Calculated Baud Rate = 16000000/(64 (25 + 1))
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
TABLE 17-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTA2
CSRC
TX9
TXEN SYNC
RCSTA2
SPEN
RX9
SREN CREN
SPBRG2 AUSART2 Baud Rate Generator Register
Legend: Shaded cells are not used by the BRG.
—
ADDEN
BRGH
FERR
TRMT
OERR
TX9D
RX9D
Reset
Values on
Page
63
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DS39629B-page 220
Preliminary
 2004 Microchip Technology Inc.