PIC18F6390 Datasheet, PDF (167/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
15.3.8 SLEEP OPERATION
In SPI Master mode, module clocks may be operating
at a different speed than when in Full Power mode; in
the case of the Sleep mode, all clocks are halted.
In most power managed modes, a clock is provided to
the peripherals. That clock should be from the primary
clock source, the secondary clock (Timer1 oscillator at
32.768 kHz) or the INTOSC source. See Section 2.7
“Clock Sources and Oscillator Switching” for
additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
15.3.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
15.3.10 BUS MODE COMPATIBILITY
Table 15-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 15-1: SPI™ BUS MODES
Standard SPI™
Mode Terminology
Control Bits State
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
1
0
0
1
1
1
0
There is also an SMP bit which controls when the data
is sampled.
TABLE 15-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
PIR1
—
ADIF
RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF
61
PIE1
—
ADIE
RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE
61
IPR1
—
ADIP
RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP
61
TRISC
PORTC Data Direction Register
62
TRISF
PORTF Data Direction Register
62
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
60
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
60
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI Mode.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 165