PIC18F6390 Datasheet, PDF (291/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
23.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
configuration bit.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is LP, XT, HS or HSPLL
(Crystal-based modes). Other sources do not require a
OST start-up delay; for these, Two-Speed Start-up
should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following
the time-out of the Power-up Timer after a Power-on
Reset is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits, IFRC2:IFRC0, immediately after
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting the
IFRC2:IFRC0 bits prior to entering Sleep mode.
In all other power managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
23.3.1 SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed
Start-up, the device still obeys the normal command
sequences for entering power managed modes,
including serial SLEEP instructions (refer to
Section 3.1.2 “Entering Power Managed Modes”).
In practice, this means that user code can change
the SCS1:SCS0 bit settings or issue SLEEP
instructions before the OST times out. This would
allow an application to briefly wake-up, perform
routine “housekeeping” tasks and return to Sleep
before the device starts to operate from the primary
oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
FIGURE 23-2:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
INTOSC
Multiplexer
OSC1
PLL Clock
Output
Q1
Q2
Q3
Q4
TOST⁽¹⁾
TPLL⁽¹⁾
CPU Clock
Peripheral
Clock
Program
Counter
PC
Wake from Interrupt Event
PC + 2
OSTS bit Set
Q1
Q2 Q3 Q4 Q1 Q2 Q3
1 2 n-1 n
Clock
Transition
PC + 4
PC + 6
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
 2004 Microchip Technology Inc.
Preliminary
DS39629B-page 289