PIC18F6390 Datasheet, PDF (154/412 Pages) Microchip Technology – 64/80-Pin Flash Microcontrollers with LCD Driver and nanoWatt Technology

PIC18F6390/6490/8390/8490
TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
59
RCON
IPEN SBOREN —
RI
TO
PD
POR
BOR
60
PIR1
—
ADIF
RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF
61
PIE1
—
ADIE
RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE
61
IPR1
—
ADIP
RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP
61
PIR2
OSCFIF CMIF
—
—
BCLIF HLVDIF TMR3IF CCP2IF
61
PIE2
OSCFIE CMIE
—
—
BCLIE HLVDIE TMR3IE CCP2IE
61
IPR2
OSCFIP CMIP
—
—
BCLIP HLVDIP TMR3IP CCP2IP
61
TRISC
PORTC Data Direction Register
62
TRISE
PORTE Data Direction Register
—
—
—
—
62
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
60
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
60
T1CON
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 60
TMR3H
Timer3 Register High Byte
61
TMR3L
Timer3 Register Low Byte
61
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 61
CCPR1L Capture/Compare/PWM Register 1 (LSB)
61
CCPR1H Capture/Compare/PWM Register 1 (MSB)
61
CCP1CON
—
—
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 61
CCPR2L Capture/Compare/PWM Register 2 (LSB)
61
CCPR2H Capture/Compare/PWM Register 2 (MSB)
61
CCP2CON
—
—
DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.
Note 1: These bits are unimplemented on 64-pin devices; always maintain these bits clear.
DS39629B-page 152
Preliminary
 2004 Microchip Technology Inc.